High Speed VLSI Architecture for AES-Galois/Counter Mode

Galois/Counter Mode of Operation (GCM) is a block cipher mode operation used to provide encryption and authentication using universal Hashing based on multiplication over binary Galois/Finite Field.GCM can be implemented on both hardware and software effectively and efficiently. GCM supports pipelined and parallelized implementations to have minimal computational latency in order to be useful at high data rates. However need for continual performance improvement is still presented due to continuous increase in network bandwidth and inefficiency of existing parallelization methods. This paper presents use of modified parallel GHASH module and modified key Expansion module to improve overall efficiency. GCM architecture is modeled in Verilog HDL and Simulated in Xilinx ISE. ASIC implementation is done on 130 nm CMOS technology. Test case 4 of NIST submission for Galois/Counter Mode (GCM) is also verified.